Re: [Help] Endian Problem

Michael Meissner <>
18 Sep 1998 23:07:07 -0400

          From comp.compilers

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[Help] Endian Problem (Yunseok Rhee) (1998-09-13)
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Re: [Help] Endian Problem (Michael Meissner) (1998-09-18)
Re: [Help] Endian Problem (1998-09-18)
Re: [Help] Endian Problem (1998-09-22)
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From: Michael Meissner <>
Newsgroups: comp.compilers
Date: 18 Sep 1998 23:07:07 -0400
Organization: Compilers Central
References: 98-09-039
Keywords: architecture, performance

Yunseok Rhee <> writes:
> For architectural simulation, I should deal with MIPS executable codes
> in a Pentium PC. Unfortunately, the endians between the two machines
> are different: MIPS machines adopt the big-endian but the PCs do the
> little-endian.
> In executables, the code section can be easily found and translated to
> the other endian form. But it is not easy with the read-only data or
> the initialized data sections because we cannot know what types of
> data were written to each address. To solve the problem, we consider
> reordering the bytes accessed on every load or store. Obviously,
> however, such frequent byte manipulations would degrade the
> performance.

Well it degrades it, but not all that much. For example, with the PowerPC
simulator, running on a 200 Mhz Pentium Pro, I ran dhrystone for 1000000
passes, and got the following results:

Big endian, default simulator 949,172 simulated instructions/second
Little endian, default sim 960,067 simulated instructions/second
Big endian, optimized simulator 1,067,769 simulated instructions/second
Little endian, optimized sim. 1,070,457 simulated instructions/second

The default PowerPC simulator can handle both endian cases, the
optimized simulator hardwires which endian format it is expecting (and
inlines some functions, etc.). All of the simulators involved were
compiled with egcs 1.03, and all of them use the BSWAP instruction to
swap 4 byte data inline via GCC's asm support (I don't remember if
they use XCHGB for the 16-bit case). Note, if you run on the Amd K6
as opposed to an Intel or a Cyrix (dunno about IDT's cpu), it will be
slighly slower, since the K6's BSWAP is 4 cycles, compared to Intel's
1 cycle.

> Conseqently, if any, I want to know how to generate the little-endian
> executables in MIPS machines. Though it is impossible, please let me
> know if you have any other idea with the problem.

Back when I was working on GCC on Mips machines, the switch was -EL to
go to little endian mode. You will obviously need to have the
appropriate libraries, etc.
Michael Meissner, Cygnus Solutions (Massachusetts office)
4th floor, 955 Massachusetts Avenue, Cambridge, MA 02139, USA, 617-354-5416 (office), 617-354-7161 (fax)

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