Re: Intel IA-64 Architecture

Chris Reedy wrote:


>
> The last two items where identified in the article as being designed
> to allow for expansion of basic blocks.
[...]
> Is it feasible to expect compilers to be able to do a good job of
> making use of this architecture? Is this a compiler writers nightmare
> (or dream)?


As our esteemed moderator said, there has been a lot of work done. If
you look where people from Multiflow now work, you will see that there
is a lot of work being done specifically for the IA64.


One of the problems with VLIW is code size. This is not as much a
problem anymore at the bulk level, with hard drives and memory prices
the way they are, but it does make you wonder about I-cache performance.


Given that techniques like speculative execution can be found in modern
RISC chips, given that the code locality of reference is higher on a
RISC chip than a VLIW chip, and given the current large dependence on
cache performance for total system performance, it will be interesting
to see how the IA-64 compares on performance of general purpose
programs.
--

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