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| Related articles |
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| C code .vs. Assembly code for Microcontrollers/DSPs ? ravindra@hal.com (1996-03-01) |
| Re: C code .vs. Assembly code for Microcontrollers/DSPs ? elvey@hal.com (1996-03-17) |
| Re: C code .vs. Assembly code for Microcontrollers/DSPs ? chuck@aage.mit.edu (1996-03-22) |
| Question: use FPU as simple VLIW? jenks@hevanet.com (Kevin Baker) (1996-03-27) |
| Re: Question: use FPU as simple VLIW? shubu@cs.wisc.edu (1996-03-28) |
| Re: Question: use FPU as simple VLIW? Peter.Damron@Eng.Sun.COM (1996-03-28) |
| Re: Question: use FPU as simple VLIW? khays@sequent.com (1996-04-02) |
| From: | Kevin Baker <jenks@hevanet.com> |
| Newsgroups: | comp.arch,comp.compilers |
| Date: | 27 Mar 1996 23:31:53 -0500 |
| Organization: | Intel (When not posting or emailing) |
| References: | 96-03-006 96-03-121 96-03-155 |
| Keywords: | parallel, architecture, question |
I was wondering if any ILP research has been done in the area of using
the FPU as a sort of VLIW co-processor when it was not being used for
regular FPU operations. It seems that the compiler could give some
work to the FPU, even if it were just adding numbers together. I have
a more radical transformation in mind however, where entire sections
of code would be transformed into the most reduced boolean algebra and
then from them there compiled into code that could run through the FPU
as well as the regular part of the CPU.
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