Re: The RISC penalty

meissner@cygnus.com (Michael Meissner)
30 Dec 1995 01:06:01 -0500

          From comp.compilers

Related articles
[2 earlier articles]
Re: The RISC penalty pardo@cs.washington.edu (1995-12-18)
Re: The RISC penalty pardo@cs.washington.edu (1995-12-19)
Re: The RISC penalty jbuck@Synopsys.COM (1995-12-20)
Re: The RISC penalty pardo@cs.washington.edu (1995-12-21)
Re: The RISC penalty iank@dircon.co.uk (1995-12-28)
Re: The RISC penalty dlmoore@ix.netcom.com (1995-12-28)
Re: The RISC penalty meissner@cygnus.com (1995-12-30)
Re: the RISC penalty john.r.strohm@BIX.com (1995-12-30)
Re: the RISC penalty pmk@pmk.mn.org (1995-12-31)
| List of all articles for this month |

From: meissner@cygnus.com (Michael Meissner)
Newsgroups: comp.compilers
Date: 30 Dec 1995 01:06:01 -0500
Organization: Cygnus Support
References: 95-12-063 95-12-132 95-12-144
Keywords: architecture

dlmoore@ix.netcom.com (David L Moore) writes:


| So, it sounds like one should build a RISC chip without many wasted
| bits! There is no reason why you cannot build a RISC machine with
| variable length instructions - the first RISC like machine (the CDC
| 6600) did just that. Variable length instructions make multi-issue
| harder because you first have to find the start of the instructions,
| which adds a few gate delays, but the only time this actually slows
| you down is when you just mis-predicted a branch. Otherwise, it just
| adds some real-estate to your instruction decoding logic.


Well it depends on how you view the instruction stream. True variable sized
instructions are a pain, but did it in terms of 60-bit words (ie, instructions
would not cross a word boundary, so if you wanted to use a 30-bit instruction,
and there are only 15 bits left in the word, you have to put a NOP, and start
on the next word).
--
Michael Meissner, Cygnus Support (East Coast)
Suite 105, 48 Grove Street, Somerville, MA 02144, USA
meissner@cygnus.com, 617-629-3016 (office), 617-629-3010 (fax)
--


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