Re: Compiler back-ends [Q]

> Register allocation is an amazing can of worms, and I don't know
> of any machine-generated code techniques being used there.


Actually, the PQCC compiler of Wolf, Leverit, etc had a very powerful
model for describing the registers of machines for a portable register
allocator. We use it in our CCG technology here at Harris Computer
Systems. We've used the same register allocator on diverse
architectures from the H-Series (6024 -- a 24 bit word addressable
machine where every register either overlaps part of another or has a
number of special uses or both), to modern RISC machines such as
PowerPC, 88110, etc.


The basic idea is that you have an "address space" called a storage
base. General Registers, Floating Point Registers and Stack are
examples of storage bases. A storage base is composed of storage
classes where each class consists of sets of groups elements of
storage bases that can be used more or less interchangeably for some
purpose. Thus even numbered general register pairs excluding r0,r1
might compose one storage class. Individual instructions take
operands of only specific classes. The compiler then extracts from
the machine description of operations where it can/must put variables
and temporaries.
--
Jeffrey Glen Jackson
jgj@ssd.csd.harris.com
x5483
--

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