VLIW Compilation Info needed

sjang@cs.mtu.edu (Saurabh Jang)
Fri, 17 Feb 1995 05:43:52 GMT

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VLIW Compilation Info needed sjang@cs.mtu.edu (1995-02-17)
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Newsgroups: comp.compilers
From: sjang@cs.mtu.edu (Saurabh Jang)
Keywords: optimize, question, VLIW
Organization: Michigan Technological University
Date: Fri, 17 Feb 1995 05:43:52 GMT


For my MS thesis I am considering doing research on register allocation
for limited-connectivity VLIW architecures. However my initial literature
search hasnt turned up too many papers.

About the only paper that I have been able to locate is "Partitioned Register
Files for VLIWs:A Preliminary Analysis of Tradeoffs" authored by A. Capitanio,
Nikil Dutt and A. Nicolau, which appeared in 25th Annual Intl. Symposium on
Microarchitecture, 1992.

The basic problem is this:

The ideal VLIW model assumes that the functional units are fully interconnected
with a single register file. However for a large number of functional units
this is not possible in practice because it requires too many ports for the
register file. Limited connectivity architectures have clusters of functional
units with the functional units in a given cluster being fully interconnected
to a private register file. All operations operate on values in the same
register file. There are specific move instructions to move data from one
register file to another if required. If an operation needs a value that
is stored in another register file the compiler has to insert appropriate
move operations in previous instructions. The goal is to minimize these
move operations, in order to keep inter-registerfile communication
as low as possible.

I would appreciate it if anyone could offer me pointers to previous or
ongoing research in this area.


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