3rd int wkshp Algorithms and Parallel VLSI Arch (8/94, Belgium)

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                                            ADVANCE PROGRAM AND REGISTRATION




                                                    3rd International Workshop on
                                        Algorithms and Parallel VLSI Architectures


                                                            August 29-31, 1994
                                                            Leuven - Belgium






                                                  A. CONFERENCE COMMITTEE




                                                              Chairmen


Marc Moonen Francky Catthoor
Dept. of Electrical Engineering IMEC
Katholieke Universiteit Leuven Leuven, Belgium
Leuven, Belgium catthoor@imec.be
marc.moonen@esat.kuleuven.ac.be




                                                              Members


Ed Deprettere Yves Robert
Dept. of Electrical Engineering Laboratoire LIP/IMAG
Delft University of Technology Ecole Normale Sup'erieure de Lyon
Delft, The Netherlands Lyon, France
ed@dutentb.et.tudelft.nl yrobert@ensl.ens-lyon.fr


Patrick Dewilde Lothar Thiele
Dept. of Electrical Engineering Institute of Microelectronics
Delft University of Technology Universit"at des Saarlandes
Delft, The Netherlands Saarbr"ucken, Germany
dewilde@dutentb.et.tudelft.nl thiele@ee.uni-sb.de


Patrice Quinton Joos Vandewalle
IRISA - INRIA Dept. of Electrical Engineering
Rennes, France Katholieke Universiteit Leuven
patrice.quinton@irisa.fr Leuven, Belgium
                                                                      joos.vandewalle@esat.kuleuven.ac.be




                                                  B. CONFERENCE SECRETARIAT


                          Mr. Filiep Vanpoucke
                          Department of Electrical Engineering - ESAT
                          Katholieke Universiteit Leuven
                          K. Mercierlaan 94, B-3001 Heverlee, Belgium
                          tel: +32 16 220931, fax: +32 16 221855
                          e-mail: filiep.vanpoucke@esat.kuleuven.ac.be




                                                  C. ORGANIZATION


This workshop is a continuation of two previous workshops of the same
name which were held in Pont-a-Mousson, France, June 1990, and Bonas,
France, June 1991.


The workshop is partly sponsored by the EC (BRA project 6632), the
European Association for Signal Processing (EURASIP), and the Belgian
National Fund for Scientific Research (NFWO), and is organized in
cooperation with the IEEE Benelux Signal Processing Chapter, the IEEE
Benelux Circuits and Systems Chapter, and INRIA, France.




                                                  D. PUBLICATIONS


The Final Program and Book of Abstracts will be distributed at the
time of the workshop. The proceedings will be published as a hard
cover book, soon after the workshop.




                                                  E. VENUE - HOTEL INFORMATION


The Workshop will be held in the Arenberg Castle of the Katholieke
Universiteit Leuven. Leuven is located in the centre of Belgium, only
30 km from Brussels and 20 km from Brussels International Airport.
Transportation from Brussels International Airport to Leuven will be
organized on Sunday August 28, 1994.


A block of dormitory rooms on campus has been reserved for
participants, as well as rooms in the Begijnhof Hotel (15 mins walking
distance from the workshop site), and will be held until June 30,
1994. After that date reservations will depend upon availability.




                                                  F. TECHNICAL PROGRAM


The technical program includes 1 hour invited papers, as well as
contributed papers, presented in regular presentation sessions (20
mins per paper) and short presentation sessions (10 mins per paper).
For all contributed papers, additional poster sessions will be
provided to stimulate discussion with all participants.




                                              MONDAY: PARALLEL ALGORITHMS


Invited Session


  P.A. Regalia (Ecole Nationale Superieure des Telecommunications,
          Evry, France)
          Rational subspace estimation and adaptive lossless filtering




Session 1 (regular)


  I.K. Proudler, J. McWhirter (DRA, Malvern, United Kingdom)
          Pipelining the inverse updates RLS array by algorithmic engineering


  A.-J. van der Veen (Stanford University, Stanford, USA)
          A 3-D systolic array for on-line computation of minimal rank matrix ap-
          proximants


  F.M.F. Gaston, D. Brown (Queen's University of Belfast, Belfast, United King-
          dom)
          Systolic square root Kalman filtering without feedback loops


  J. Kadlec (Queen's University of Belfast, Belfast, United Kingdom)
          Numerical analysis of normalised RGS filter by probability description of
          propagated data




Session 2 (regular)


  G.C. Cardarilli, R. Lojacono, M. Re, M. Salerno (University of Rome - Tor
          Vergata, Rome, Italy)
          Efficient VLSI architecture for residue to binary converter


  G.O. Glentis, Ilias Bouras, N. Kalouptsidis (University of Twente, Twente,
          The Netherlands)
          Efficient VLSI architectures for block Toeplitz and Toeplitz like systems


  F. Vanpoucke, M. Moonen (Katholieke Universiteit Leuven, Leuven, Belgium)
          An array for stable spherical subspace tracking


  A. Drummond, I.S. Duff, D. Ruiz (CERFACS, Toulouse, France)
          Parallel block iterative solvers for heterogeneous computing environments




Session 3 (short)


  J. Champeau, B. Pottier, L. Le Pape (Universite de Bretagne Occidentale,
          Brest, France)
          Parallel grep


  J. Dehaene, M. Moonen, J. Vandewalle (Katholieke Universiteit Leuven, Leu-
          ven, Belgium)
          A continuous time approach to the analysis and design of parallel algo-
          rithms for subspace tracking


  N. Saxena and J.J. Clark (Harvard University, Cambridge, USA)
          Parallel implementation of the double bracket matrix flow for eigenvalue-
          eigenvector computation and sorting


  J. Goetze, G.J. Hekstra (Technische Universitaet Muenchen, Germany)
          Adaptive approximate rotations for EVD and SVD


  J. Schier (Institute of Information Theory and Automation, Prague, Czech
          Republic)
          A block-regularized identification with an inverse update




                                      TUESDAY: PARALLEL ARCHITECTURES


Invited Session


  K. Vissers (Philips, Eindhoven, The Netherlands)
          Architecture and Programming of Parallel Video Signal Processors




Session 4 (regular)


  C.A. Christopoulos, A.N. Skodras, J. Cornelis (Vrije Universiteit Brussel,
          Brussels, Belgium)
          Modelling the 2-D FCT on a multiprocessor system


  E. De Greef, F. Catthoor, H. De Man (IMEC, Leuven, Belgium)
          A memory efficient, programmable multi-processor architecture for real-
          time motion estimation type algorithms


  K. Roenner, J. Kneip, P. Pirsch (Universitaet Hannover, Hannover, Germany)
          A highly parallel single-chip video signal processor


  T. Duboux, A. Ferreira, M. Gastaldo (Ecole Nationale Superieure de Lyon,
          Lyon, France)
          A scalable design for dictionary machines




Session 5 (regular)


  J. Rosseel, F. Catthoor, T. Gijbels, P. Six, L. Van Gool, H. De Man (IMEC,
          Leuven, Belgium)
          An optimisation methodology for mapping a diffusion algorithm for vision
          into a modular and flexible array architecture


  D.K. Arvind, V.E. Rebello (University of Edinburgh, Edinburgh, United King-
          dom)
          Distributing control in superpipelined VLSI architectures


  H. Van Dijck, E.F. Deprettere, G.J. Hekstra (Delft University of Technology,
          Delft, The Netherlands)
          Scalable parallel processor array for Jacobi-type matrix computations


  C. Riem, J. Koenig, L. Thiele (Universitaet des Saarlandes, Saarbruecken,
          Germany)
          A case study in algorithm-architecture codesign: hardware-accelerator for
          long integer operations




Session 6 (short)


  J. van Kats (CONVEX computer BV, Utrecht, The Netherlands)
          CONVEX exemplar systems scalable parallel processing


  M. Hall, A. Astroem (Linkoeping University, Linkoeping, Sweden)
          High speed wood inspection using a parallel VLSI architecture


  M. Schwiegershausen, M. Schoenfeld, P. Pirsch (Universitaet Hannover, Han-
          nover, Germany)
          Mapping complex image processing algorithms onto heterogeneous multi-
          processors regarding architecture dependent performance parameters


  D. Archambaud, I. Saraiva Silva, L. Winckel, P. Faudemay, J.Penne, A. Greiner
          (Universite Pierre et Marie Curie, Paris, France)
          Systolic implementation of Smith and Waterman algorithm on a SIMD
          coprocessor


  P. Held, B. Kienhuis (Delft University of Technology, Delft, The Netherlands)
          DIV, FLOOR, CEIL, MOD and STEP functions in nested loop programs
          and linear bounded lattices


  D.D. Manohar, G.B. Singh (Wayne State University, Detroit, USA)
          VLSI architecture of a matrix transformation multiprocessor




                                      WEDNESDAY: PARALLEL COMPILATION


Invited Session


  P. Feautrier (Laboratoire PRiSM-CNRS, Versailles, France)
          Compiling for massively parallel architectures: a perspective




Session 7 (regular)


  L. Rapanotti, G.M. Megson (University of Newcastle upon Tyne, Newcastle
          upon Tyne, United Kingdom)
          Uniformisation techniques for reducible integral recurrence equations


  C. Reffay, G.-R. Perrin (Universite de Franche-Comte, Besancon, France)
          From dependence analysis to communication code generation: the "look
          forwards" model


  V. Bouchitte, P. Boulet, A. Darte, Y. Robert (Ecole Nationale Superieure de
          Lyon, Lyon, France)
          A model of evaluation of array expressions on state of the art massively
          parallel machines


  M.R. Werth, P. Feautrier (Laboratoire PRiSM-CNRS, Versailles, France)
          Some limiting factors for the generation of efficient
          compiler-parallelized programs


Session 8 (short)


  H.-K. Kim (ETRI, Daejeon, Korea)
          Optimal communication for a graph based DSP silicon compiler


  P. Luksch (Technische Universitaet Muenchen, Muenchen, Germany)
          A portable testbed for evaluating different approaches to
          distributed logic simulation


  G. Durrieu, M. Lemaitre (ONERA/CERT/DERI, Toulouse, France)
          Design by Transformation of Synchronous Descriptions


  F. Sanchez, J. Cortadella (Universitat Politecnica de Catalunya, Barcelona,
          Spain)
          Resource-constrained software pipelining for high-level synthesis of DSP
          systems


  N. Langloh, M. Mertens, J. Cornelis (Vrije Universiteit Brussel, Brussels,
          Belgium)
          A simulator for optical parallel computer architectures


  R. Rangaswami (University of Edinburgh, Edinburgh, United Kingdom)
          Higher-order programming constructs for distributed-memory machines




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                                                ADVANCE REGISTRATION FORM


                                            3rd International Workshop on
                                Algorithms and Parallel VLSI Architectures




Professional Title ____________________________________________________


Name ____________________________ First Name __________________________


Affiliation ___________________________________________________________


Mailing Address _______________________________________________________


  ______________________________________________________________________


  ______________________________ Country _______________________________


Phone __________________ Telex __________________ Fax _________________


E-Mail address ________________________________________________________




EURASIP member number _________________________________________________






                                                              Before 30/6 After 30/6


  EURASIP Member Registration (*) 12.500 BEF 15.000 BEF = _________ BEF


  Non-Member Registration 15.000 BEF 17.500 BEF = _________ BEF


  Student Registration (**) 10.000 BEF 12.500 BEF = _________ BEF


  Dormitory Room (per night) (***) 800 BEF 1.000 BEF = _________ BEF


  TOTAL = _________ BEF


BEF: Belgian Franks.


(*) Society members must include their membership number to qualify
            for a discount.


(**) No proceedings. Students must include tutor's endorsement.


(***) Includes Breakfast. Arrival date ___________ Departure Date ____________




Registration fees include : workshop sessions, proceedings (except for
student registration), refreshments, all lunches and dinners. If the
advance registration form and reduced rate payment are received after
30/6, you are requested to pay the balance during on-site
registration. In case of cancellation, 80 % of the registration fee
will be refunded, up to 31/7. The cost of the conference proceedings
will be deducted from the refund.




PAYMENT


  O I enclose a check/bank draft made payable to
                                K.U.Leuven - ESAT/Workshops
                                K. Mercierlaan 94, B-3001 Leuven, Belgium


  O I choose to pay by Bank transfer to account 001-2358242-54
        at ASLK - CGER Bank
                                Wolvengracht 48, B-1000 Brussels, Belgium
        of K.U.Leuven - ESAT/Workshops
                                K. Mercierlaan 94, B-3001 Leuven, Belgium
        (all costs to sender)




Date ______________________ Authorized Signature ____________________________




Please return this form to


                    Mr. Filiep Vanpoucke
                    Katholieke Universiteit Leuven
                    Dept. of Electrical Engineering - ESAT
                    K. Mercierlaan 94, B-3001 Leuven, Belgium,
                    Fax: +32 16 221855.




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                                                    HOTEL RESERVATION FORM


                                            3rd International Workshop on
                                Algorithms and Parallel VLSI Architectures




Specially discounted rooms have been reserved at the Begijnhof Congres
Ho- tel, located between the city centre and the campus (15 mins walk
from the Workshop site), and will be held until June 30. After that
date reservations will depend upon availability. Telephone
reservations will not be accepted. Prices include breakfast, service,
VAT and city tax.




Name ___________________________ First Name __________________________


Company name/Institution _____________________________________________


Mailing Address ______________________________________________________


  _____________________________________________________________________


  ______________________________ Country ______________________________


Phone __________________ Telex ________________ Fax __________________


Arrival date _________________________ Time __________________________


Departure date _______________________ Time __________________________




                      O Single room (3700 BEF per night)
                      O Double room (4300 BEF per night)


In order to guarantee your reservation, please advise a valid credit
card number and expiration date. In case of no-show, 75 % of the price
will be charged.


                      O American Express
                      O Diners Club
                      O Eurocard/Mastercard
                      O Visa


Card No _______________________ Expiration Date ______________________


Name as it appears on credit card ____________________________________


Date _____________________ Authorized Signature ______________________




Please return to:


                                          Begijnhof Congres Hotel
                                          Tervuursevest 70
                                          B-3000 Leuven, Belgium
                                          Tel: +32 16 291010
                                          Fax: +32 16 291022




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================================================================================
Lode Nachtergaele
IMEC V.Z.W.
Kapeldreef 75 Small
3001 Heverlee is
Belgium beautiful
E-mail: nachterg@imec.be
Phone : +32 (0)16 28.15.12
Fax : +32 (0)16 28.15.15
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