"Delayed" instructions on the MIPS/SPIM simulator

Joe Hummel <jhummel@cy4.ICS.UCI.EDU>
Sat, 21 May 1994 06:26:34 GMT

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Related articles
"Delayed" instructions on the MIPS/SPIM simulator jhummel@cy4.ICS.UCI.EDU (Joe Hummel) (1994-05-21)
Re: "Delayed" instructions on the MIPS/SPIM simulator larus@cs.wisc.edu (1994-05-23)
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Newsgroups: comp.compilers,comp.arch
From: Joe Hummel <jhummel@cy4.ICS.UCI.EDU>
Keywords: architecture, tools, question
Organization: UC Irvine, Department of ICS
Date: Sat, 21 May 1994 06:26:34 GMT

We're using the SPIM simulator (freely available from Prof. Larus at the
U. of Wisconsin) in an undergraduate architecture class. I'd like the
students to have a chance to use the delayed branch and load instructions
available on the MIPS. The SPIM manual mentions how this is generally
hidden from the user unless you run in "bare" hardware mode. But once I'm
running in bare mode, it isn't clear to me which instructions now become
the delayed ones. Or are the delayed instructions an entirely different
set of opcodes? And what restrictions limit the choice of instructions
for filling a delay slot?

Any help would be greatly appreciated... Thanks in advance,

    - joe hummel
Joe Hummel
ICS Graduate Student, UC Irvine
Internet: jhummel@ics.uci.edu

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