Re: optimizing for caches

preston@miranda.cs.rice.edu (Preston Briggs)
Thu, 19 Nov 1992 17:43:02 GMT

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optimizing for caches richard@meiko.com (Richard Cownie) (1992-11-17)
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Newsgroups: comp.compilers
From: preston@miranda.cs.rice.edu (Preston Briggs)
Organization: Rice University, Houston
Date: Thu, 19 Nov 1992 17:43:02 GMT
References: 92-11-098
Keywords: optimize, architecture,

Richard Cownie <richard@meiko.com> writes:
>From experiences tuning vector routines for i860's and SPARC's, I've come
>to the conclusion that understanding and exploiting the memory hierarchy
>is essential to obtain good performance on these kinds of problems. But I
>have yet to see a compiler which tackles this aspect of optimization.


I agree that the problem is terribly important. On the other hand,
Portland Group's compiler for the i860 certainly attacks the problem, as
does the Kuck preprocessor that is so maligned in discussions of the SPEC
benchmarks. Additionally, there are several research compilers attacking
these problems (at Stanford, Rice, Illinois, and other places).


There's been a lot of research in the area. I don't have a good
bibliography for this area; but, a nice starting point might be


The Cache Performance and Optimization of Blocked Algorithms
Monica Lam, Edward E. Rothberg, and Michael E. Wolf
pages 63-74
ASPLOS IV, 1991


Preston Briggs
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