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| Related articles |
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| [2 earlier articles] |
| Re: Register Files ssimmons@convex.com (1992-10-06) |
| Re: Register Files cliffc@cs.rice.edu (1992-10-06) |
| Re: Register Files hobbs@steven.enet.dec.com (1992-10-06) |
| Re: Register Files kendall@centerline.com (1992-10-07) |
| Re: Register Files bart@cs.uoregon.edu (1992-10-07) |
| Re: Register Files henry@zoo.toronto.edu (1992-10-07) |
| Re: Register Files ali@LARK.WARP.CS.CMU.EDU (Ali-Reza Adl-Tabatabai) (1992-10-22) |
| Re: Register Files idacrd!desj@uunet.UU.NET (1992-10-23) |
| Newsgroups: | comp.compilers |
| From: | Ali-Reza Adl-Tabatabai <ali@LARK.WARP.CS.CMU.EDU> |
| Organization: | Compilers Central |
| Date: | Thu, 22 Oct 1992 14:29:29 GMT |
| References: | 92-10-019 |
| Keywords: | registers, architecture |
Having split register files also makes superscalar dispatch simpler. The
dispatch stage need only check if the instructions are destined for
different FU classes (integer, FP, etc...), without checking for register
dependences (except for load and moves between register files). For
example in the IBM RS6000, there is the FP, integer and condition code
registers. Instructions in the instruction window that are destined for
different functional units can be issued in parallel (e.g. a decoupled
architecture).
Ali
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