Related articles |
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[5 earlier articles] |
Re: Register Allocation and Aliasing mike@vlsivie.at (1990-07-15) |
Re: Register Allocation and Aliasing aglew@dwarfs.crhc.uiuc.edu (1990-07-16) |
Re: Register Allocation and Aliasing phorgan@cup.portal.com (Patrick Horgan) (1990-07-17) |
Re: Register Allocation and Aliasing heggy@cs.pitt.edu (1990-07-17) |
Re: Register Allocation and Aliasing aglew@oberon.crhc.uiuc.edu (1990-07-17) |
Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
Re: Register Allocation and Aliasing vestal@src.honeywell.com (1990-07-19) |
Newsgroups: | comp.compilers |
From: | lupine!rfg@uunet.UU.NET (Ron Guilmette) |
Keywords: | code, optimize |
Organization: | Network Computing Devices, Inc., Mt. View, CA |
References: | <1990Jul17.124057.1688@esegue.segue.boston.ma.us> |
Date: | Thu, 19 Jul 90 18:21:38 GMT |
In article <1990Jul17.124057.1688@esegue.segue.boston.ma.us> Patrick Horgan <phorgan@cup.portal.com> writes:
>On Amdahl machines a data read or write to cache or register takes only
>one cycle. There is no difference.
Gee! I guess that Amdahl's *never* get cache misses!
Now why didn't anybody mention that to me when I worked there? ;-)
--
// Ron Guilmette (rfg@ncd.com)
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