Re: Register Allocation and Aliasing

>IT EVEN HAS A NAME: it's called ``cache memory''. Access times are short
>and if integrated on the chip can be as fast as a register access.


As I am sure Mr. Gschwind knows, cache implemented on-chip is not as
fast as register access, chiefly because cache is seldom multiported,
as well as for other reasons such as loading, and the number of
addresses that can be specified in an instruction.


If you will, we are talking about the space formed by the
cross-product of the following parameters:


        ADDRESSING = by memory address and/or by register number


        MULTIPORTING = 1r/w .. 2r/1w ...


        SIZE/SPEED = large/slow .. small/fast


The standard configurations are


        CACHE = addressed by memory address (associatively)
         single-ported
         large/slow (at least wrt. registers)


        REGISTER = addressed by number
         multiported
         small/fast


What I was asking about, and what Hank Dietz et al, and others, have
explored, is whether there are other configurations between these two
extremes that might be useful.


--
Andy Glew, aglew@uiuc.edu
--

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