Related articles |
---|
Register Allocation and Aliasing aglew@oberon.crhc.uiuc.edu (1990-07-05) |
Re: Register Allocation and Aliasing rfg@ncd.com (1990-07-06) |
Re: Register Allocation and Aliasing preston@rice.edu (Preston Briggs) (1990-07-14) |
Re: Register Allocation and Aliasing pur-ee!hankd@dynamo.ecn.purdue.edu (1990-07-14) |
Re: Register Allocation and Aliasing torbenm@diku.dk (1990-07-14) |
Re: Register Allocation and Aliasing mike@vlsivie.at (1990-07-15) |
Re: Register Allocation and Aliasing aglew@dwarfs.crhc.uiuc.edu (1990-07-16) |
Re: Register Allocation and Aliasing phorgan@cup.portal.com (Patrick Horgan) (1990-07-17) |
Re: Register Allocation and Aliasing heggy@cs.pitt.edu (1990-07-17) |
Re: Register Allocation and Aliasing aglew@oberon.crhc.uiuc.edu (1990-07-17) |
Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
[1 later articles] |
Newsgroups: | comp.arch,comp.compilers |
From: | mike@vlsivie.at (Inst.f.Techn.Informatik) |
Followup-To: | comp.arch,comp.compilers |
Keywords: | optimize,code |
Organization: | Technical University of Vienna, AUSTRIA |
References: | <1990Jul06.194618.4957@esegue.segue.boston.ma.us> |
Date: | Sun, 15 Jul 90 20:56:06 GMT |
In article <1990Jul06.194618.4957@esegue.segue.boston.ma.us>, rfg@ncd.com (Ron Guilmette) writes:
> In article <1990Jul05.155937.13214@esegue.segue.boston.ma.us> you write:
> >...
> > Hare brained idea: allocate quantities that *might* be aliased to
> >registers anyway. Provide a register to contain the true memory
> >address of the aliased quantity, ...
>
> Actually, this sounds like a marvelous idea to me!
It most certainly is a marvelous idea! And it works! And it has been
implemented. Here a short description:
As opposed to the suggestions made in these postings, there is no overhead
vor loading the addresses associated with extra instructions into breakpoint
registers. It is done automagically. It also uses a dynamic allocation
scheme for the register values and can use *LOTS* of registers
(Anywhere from 8 KB to 64KB).
IT EVEN HAS A NAME: it's called ``cache memory''. Access times are short
and if integrated on the chip can be as fast as a register access.
bye,
mike :-)
Michael K. Gschwind mike@vlsivie.at
Technical University, Vienna mike@vlsivie.uucp
Voice: (++43).1.58801 8144 e182202@awituw01.bitnet
Fax: (++43).1.569697
--
Return to the
comp.compilers page.
Search the
comp.compilers archives again.