Re: 8086 register allocation

gah4 <gah4@u.washington.edu>
Mon, 10 May 2021 14:49:27 -0700 (PDT)

          From comp.compilers

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Re: 8086 register allocation gah4@u.washington.edu (gah4) (2021-05-10)
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From: gah4 <gah4@u.washington.edu>
Newsgroups: comp.compilers
Date: Mon, 10 May 2021 14:49:27 -0700 (PDT)
Organization: Compilers Central
References: 21-05-005
Injection-Info: gal.iecc.com; posting-host="news.iecc.com:2001:470:1f07:1126:0:676f:7373:6970"; logging-data="32173"; mail-complaints-to="abuse@iecc.com"
Keywords: code, registers
Posted-Date: 10 May 2021 18:12:50 EDT
In-Reply-To: 21-05-005

On Sunday, May 9, 2021 at 5:04:18 PM UTC-7, alexf...@gmail.com wrote:
> For the fun of it I've implemented a greedy bottom-up local register
> allocator for the intel 8086 CPU, which is known for its non-uniform
> use of registers in ALU instructions and memory operands
> (https://github.com/alexfru/regal86).


Reminds me of what, as far as I know, is also an unsolved problem:
register allocation for the x87.


First the 8087 was designed not knowing if it should be a stack or
register machine, so stack registers are addressable. (Even though
the addresses keep changing.)


It was also designed to have a virtual stack, which would spill to memory
on overflow, and back on underflow. That sounds nice, but it seems that
no-one tried to write the interrupt routine before the hardware was built,
and that it actually isn't possible. It seems that it isn't possible to get some
of the state bits set, such that it all works like a seamless virtual stack.


The 80287 is the same processing logic with a different bus interface
(and separate clock). As well as I know, things were redesigned later,
but it seems that there still is no virtual stack.


There are description of some compilers that give up on compiling any
code that needs more than eight registers.


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