Call for papers - AMAS-BT'2015 joint with CGO - Architectural and Microarchitectural Support for Binary Translation (Burlingame, Feb 15)
Fri, 31 Oct 2014 13:09:00 -0700 (PDT)

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Call for papers - AMAS-BT'2015 joint with CGO - Architectural and Micr (2014-10-31)
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Newsgroups: comp.compilers
Date: Fri, 31 Oct 2014 13:09:00 -0700 (PDT)
Organization: Compilers Central
Keywords: conference, translator, CFP
Posted-Date: 31 Oct 2014 16:33:35 EDT

AMAS-BT 2015 (
8th Workshop on Architectural and Microarchitectural Support for Binary
Co-located with CGO 2015 (

San Francisco Bay Area, CA
February 7, 2015

Abstracts Due: December 7, 2014
Full Submissions Due: December 14, 2014
Notification of Acceptance: Early January

Long employed by industry, large scale use of binary translation and
on-the-fly code generation is becoming pervasive both as an enabler for
virtualization, processor migration and also as processor implementation
technology. The emergence and expected growth of just-in-time compilation,
virtualization and Web 2.0 scripting languages brings to the forefront a need
for efficient execution of this class of applications. The main goal of this
half-day workshop is to bring together researchers and practitioners with the
aim of stimulating the exchange of ideas and experiences on the potential and
limits of Architectural and MicroArchitectural Support for Binary Translation
(hence the acronym AMAS-BT).

The key focus is on challenges and opportunities for such assistance and
opening new avenues of research. A secondary goal is to enable dissemination
of hitherto unpublished techniques from commercial projects. We invite authors
to submit previously unpublished work that incorporates:

Dynamic compilation and architectural interaction:
        - Just-In-Time compilation: efficiency, persistence, ahead-of-time
        - Efficient bytecode translation issues
        - Efficient ISA representation for dynamic compilation
        - Efficient compilation methods
Binary translation: Architectural effects and experience:
        - Novel applications of binary translation and virtualization
        - Performance characterization
        - Dynamic instrumentation and debugging
        - HW/SW co-design for efficient execution
        -Experimental insights and industrial experience

Hardware assistance for optimization:
        - Extra/enhanced internal/physical registers
        - Speculative execution support
        - Reduced footprint/low-power cores enabled by binary translation, area
and power efficiency
        - Techniques for parallelizing single-threaded programs
Hardware assistance for translation and code discovery:
        - Interpretation, decoding assistance, code dispatch
        - On-the-fly reconstruction of CFGs, data dependences, scheduling and
        - Bug-per-bug compatibility issues
        - Static and hybrid (runtime-assisted) translation
Binary translation: Heterogeneous cores and applications:
        - Dynamic code targeting heterogeneous architectures
        - Dynamic parallelization, vectorization
        - Power-efficient execution
        - CPU-GPU code migration
        - Novel architectures, memory systems and caching for CPU/GPU

Hardware assistance for runtime management:
        - Self-modifying/self-referential code, precise exceptions
        - Runtime profiling: branches, caches, memory accesses
        - Management of translated code
        - Adapting code to changing program behavior
        - Persistent translation, incremental translation

In order to submit a paper to AMAS-BT 2015 authors should use Easy Chair
( If you do not already
have an EasyChair account, you can generate one using the same link. Click on
*New Submission*, and then follow the instructions to submit your paper. You
can return later to update your submission. EasyChair will send you an e-mail
message confirming your submission. Please remember that AMAS-BT 2015 uses a
two phase submission process. You will first submit the abstract of your
paper, and later the final manuscript (please check the important dates
below). Submissions should about six pages or 5,000 words, in IEEE style,
2-column, 10-point text using .doc, .pdf, or .ps. formats. Templates can be
found at:

Mauricio Breternitz, AMD
Vijay Janapa Reddi, The University of Texas at Austin

Matthew Halpern, The University of Texas at Austin

Aaron Smith, Microsoft Research
David Kaeli, Northeaster University
Wei Chung Hsu, National Chaio Tung University
Chenggang Wu, Institute of Computing Technology Chinese Academy of Sciences
Edson Borin, University of Campinas
Evelyn Duesterwald, IBM T.J. Watson Research Center
Robert Cohn, Intel Corporation
Rodrigo Domingues, Qualcomm
Anton Chernoff, Nvidia

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