Call For Papers - AMAS-BT 2009 joint with ISCA 2009 2nd Workshop on Architectural and Microarchitectural Support for Binary Translation (Austin TX, Jun 09)

CALL FOR PAPERS -- AMAS-BT 2009


2nd Workshop on Architectural and Microarchitectural Support for
Binary Translation


Held in conjunction with the 36th Int'l Symposium on Computer
Architecture (ISCA-36)


Austin, Texas -- June 20, 2009


http://amas-bt.cs.virginia.edu/
Workshop Overview


Long employed by industry, large scale use of binary translation and
on-the-fly code generation is becoming pervasive both as an enabler
for virtualization, processor migration and also as processor
implementation technology. The emergence and expected growth of just-
in-time compilation, virtualization and Web 2.0 scripting languages
brings to the forefront a need for efficient execution of this class
of applications. The availability of multiple execution threads brings
new challenges and opportunities, as existing binaries need to be
transformed to benefit from multiple processors, and extra processing
resources enable continuous optimizations and translation.


The main goal of this half-day workshop is to bring together
researchers and practitioners with the aim of stimulating the exchange
of ideas and experiences on the potential and limits of Architectural
and MicroArchitectural Support for Binary Translation (hence the
acronym AMAS-BT). The key focus is on challenges and opportunities for
such assistance and opening new avenues of research. A secondary goal
is to enable dissemination of hitherto unpublished techniques from
commercial projects.


The workshop scope includes support for decoding/translation, support
for execution optimization and runtime support. It will set a high
scientific standard for such experiments, and requires insightful
analysis to justify all conclusions. The workshop will favor
submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the
proposed technique performs as the results indicate.
Submission Topics


Hardware assistance for translation and code discovery:


        * Interpretation engines, decoding assistance, translated code
dispatch
        * On-the-fly reconstruction of CFGs and data dependences,
scheduling and optimization
        * Bug-per-bug compatibility issues
        * Static translation: without runtime assistance/translation and
with runtime assistance/translation (Hybrid Translation)


Hardware assistance for optimization:


        * Extra/enhanced internal/physical registers
        * Speculative execution support
        * Reduced footprint/low-power cores enabled by binary translation,
area and power efficiency
        * Techniques for parallelizing single-thread programs


Hardware assistance for runtime management:


        * Self-modifying code, self-referential code, precise exceptions
        * Runtime information: profiling branch directions, instructions
with cache misses, memory access monitoring
        * Management of translated code and adapting code to changing
program behavior, persistent translation, incremental translation
        * Multi-many cores: parallel translation, auto parallelization,
speculative execution


Binary Translation: Architectural effects and experience:


        * Novel applications of binary translation and virtualization
        * Performance characterization
        * Dynamic instrumentation and debugging
        * HW/SW co-design for efficient execution
        * Experimental insights on binary translation and industrial
experience


How to Submit


Please email Mauricio Breternitz: mauricio DOT breternitz DOT jr AT
intel DOT com


        * abstract of about 200 words in plain text format, along with
title, authors, and contact email, by April 15, 2009
        * publication-ready submission of no more than 5000 words in IEEE
style, 2-column, 10-point text in .doc, .pdf, or .ps format, by April
22, 2009


Submissions will be acknowledged via return email within 48 hours.
Important Dates


        * Abstract due: April 15, 2009
        * Submission: April 22, 2009
        * Notification of acceptance: May 2009


Workshop Organizers


        * Mauricio Breternitz, Intel
        * Robert Cohn, Intel
        * Michael Gshwind, IBM
        * Youfeng Wu, Intel


Program Committee


        * Erik Altman, IBM
        * Mauricio Breternitz, Intel
        * Mark Charney, Intel
        * Robert Cohn, Intel
        * Andy Glew, Intel
        * Michael Gshwind, IBM Research
        * Kim Hazelwood, University of Virginia
        * David Kaeli, Northeastern University
        * Chris J. Newburn, Intel
        * Alex Skaletsky, Intel
        * Chenggang Wu, CAS, China
        * Youfeng Wu, Intel

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