Instruction pipe line delay?

Hi all


I would like to get any thoughts/experience/suggestion, regarding C
compiler (gcc) for following pipeline processor arch.


We got a "embedded" processor which has one delay slot for any
internal ALU operations and two delay slots for branch and memory load
instructions, see below example. This is due to hardware throughput
requirements. And its resonably easy to schedule instructions to
minimize NOPs when we are doing assembler codes.


However, where I'm a bit clueless is "can we get c compiler (gcc) to
schedule instructions, to minimize NOPs?". Better still "can somone
comment on whats the expected average NOP percentage for such arch,
for a typical C code ?". I know its a very open question and depends
on lots of things.. but any clue/comments are wellcome.


I'm wondering whether to implement hardware resource conflict check or
not. NOPs are not only bubbles in pipeline it increases program memory
foot print and increase power as well, so I need help from high level
language prospective.


Any pointers to reading materials would be much appreciated as well.


Thanks in advance.




ALU instruction, one delay slot
===========


ADD r1 r2 r3
NOP ; required NOP due to ALU delay slot for r1
AND r2 r1 r4


Memory Load instruction, two delay slots
==================


LDW r1 r2
NOP
NOP
ADD r3 r1 r4


Branch instruction, two delay slots
==============


BEQ Lable
NOP ; executed regardless of branch is taken or not
NOP ; executed regardless of branch is taken or not

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