Re: Software Pipelining

Touati Sid <sidtouati@inria.fr>
Mon, 08 Sep 2008 14:25:13 +0200

          From comp.compilers

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Re: Software Pipelining mr.neeraj@gmail.com (Neeraj Goel) (2008-09-02)
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[3 later articles]
| List of all articles for this month |

From: Touati Sid <sidtouati@inria.fr>
Newsgroups: comp.compilers
Date: Mon, 08 Sep 2008 14:25:13 +0200
Organization: Universite de Versailles Saint-Quentin-en-Yvelines
References: 08-08-072 08-08-086 08-08-092 08-08-098 08-09-016
Keywords: optimize
Posted-Date: 09 Sep 2008 04:07:55 EDT

Neeraj Goel a icrit :


> Also, the overheads of modulo scheduling can make it worse.
> Overheads include, more registers, prolog and epilog instructions.
> As Tim said, only advantage is in hiding latencies such as memory
> access and floating point.


Software pipelining is usually beneficial for loops with a high number
of iterations.


S


ps: In order to hide memory latencies, non blocking caches should be
present in the underlying cpu. This is not common in vliw processors.



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