Re: Coding a translator between languages with high abstraction levels

On 11/7/2006 9:18 PM, Alfonso Acosta wrote:


> I'm a computer science engineering student, writing his masters thesis
> about a VHDL translator for ForSyDe
> (http://www.imit.kth.se/info/FOFU/ForSyDe/ , a Hardware Description
> Language embedded in Haskell, http://www.haskell.org/ ).
>
> I don't have much experience in compiler design and development apart
> from a toy Pascal compiler I had to code for an undergraduate compiler
> course.


Peter Reinjtes wrote a VHDL parser and pretty-printer in Prolog some
years ago (it also produced images using PostScript, IIRC). A quick
websearch found this:
http://www.cs.wright.edu/people/faculty/tkprasad/VHDL/


"The original VHDL-87 parser was developed in conjunction with
software components for schematic entry, logic synthesis, and a
universal hardware description language translator." By taking
advantage of Prolog's conciseness, it is "between one tenth and one
fifth the size of other VHDL implementations."


There's a related article here ("PREDITOR: A Prolog-Based VLSI
Editor"):
http://mitpress.mit.edu/catalog/item/default.asp?ttype=2&tid=3509


Because Prolog is declarative (if written carefully), the VHDL
translator can work either VHDL->target or target->VHDL.

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