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| Related articles |
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| [5 earlier articles] |
| Re: Register allocation dany42NOSPAM@free.fr (Dan) (2003-07-21) |
| Re: Register allocation sumesh_uk@hotmail.com (2003-07-31) |
| Register allocation avizit@gmail.com (2004-07-15) |
| Re: Register allocation gopi@sankhya.com (2004-07-28) |
| Re: Register allocation rajaram@acmet.com (Rajaram) (2004-08-04) |
| Re: Register allocation kamalp@acm.org (2004-08-05) |
| Re: Register allocation kym@sdf.lonestar.org (russell kym horsell) (2004-08-09) |
| Re: Register allocation kamalp@acm.org (2004-08-09) |
| Re: Register allocation gopi@sankhya.com (2004-08-10) |
| Re: Register allocation anton@mips.complang.tuwien.ac.at (2004-08-10) |
| Re: Register allocation anton@mips.complang.tuwien.ac.at (2004-08-10) |
| Re: Register allocation kym@kymhorsell.com (2004-08-11) |
| Re: Register allocation kamalp@acm.org (2004-08-13) |
| [17 later articles] |
| From: | russell kym horsell <kym@sdf.lonestar.org> |
| Newsgroups: | comp.compilers |
| Date: | 9 Aug 2004 01:12:20 -0400 |
| Organization: | Central Iowa (Model) Railroad, Plano, TX, USA |
| References: | 04-07-044 04-07-074 04-08-022 |
| Keywords: | registers, code |
| Posted-Date: | 09 Aug 2004 01:12:20 EDT |
Kamal R. Prasad <kamalp@acm.org> wrote:
[...]
> The overhead is 1-load and 1-store, but the overhead isn't as high as
> you would expect, thanks to a hierarchy of caches to speed things up.
> No doubt the speed with which a register can be accessed is much
[...]
Measure it, and you'll get a shock. On 5 yo architecture there seems
to be virtually no diff between memory access and registers for common
stuff. That and the h/w scheduling of instrs makes efficient code gen
a bit easier. ;-)
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