JEC Special Issue on Data Cache Analysis and Optimizations for Embedded Systems

                                                  CALL FOR PAPERS


                              Journal of Embedded Computing (JEC)


                                                    Special Issue
                                                              on


        Data Cache Analysis and Optimizations for Embedded Systems




SCOPE
=====


As data sets processed by embedded processors increase in size and
complexity, data caches become crucial for achieving high performance
and low power consumption. Today's general-purpose mid- to high-end
embedded processors are generally equipped with data caches to bridge
the ever-increasing performance gaps between the processor and
off-chip memories. However, data caches are effective only for
applications that exhibit sufficient data locality in their memory
accesses. Applications with excessive cache misses often suffer from
poor performance and energy efficiency. Furthermore, data cache
behavior is inherently unstable, making it difficult to conduct
effective cache behavior analysis and optimisations.


Unlike in the case of general-purpose desktop systems, power consumption
is especially important in battery-operated embedded systems and is also an
important design constraint where power supply is limited. In addition,
embedded systems are designed to run a set of well-defined applications,
which can be highly tuned by the application programmer. In the past few
years, a number of cache analysis techniques, energy-aware compiler
cache optimizations and energy-efficient cache architectures have been
developed for predicting data cache behavior, improving data cache
performance and reducing data cache energy consumption.


This special issue seeks original and unpublished work of theoretical
or practical emphasis in the area of data cache analysis and
optimizations for embedded systems, including but are not limited to:


o Compiler optimizations for improving data cache performance and power consumption
o Code generation considering data caches
o Data layout transformations
o Data compression transformations
o Data cache behavior analysis
o Timing and schedulability analysis by modeling data caches
o Data cache management in hard real-time systems
o Energy-efficient cache architecture
o Reconfigurable cache architecture
o Application case studies




IMPORTANT DATES
===============


Expression of Interest: 1 July, 2004
Submission Deadline: 1 August, 2004
Acceptance Notification: 1 November, 2004
Final Manuscript: 1 December, 2004
Publication Date: January-February, 2005




GUIDELINES FOR SUBMISSION
=========================


-- Prospective authors should follow the IEEE Transaction
      manuscript format described in the Guide for Authors at:


                                http://juliet.stfx.ca/~jec/


      Please limit your paper to approximately 15 pages in length.


-- Your email of intent to submit a paper should include
        author(s) information, a title and an abstract.


-- Please email your submission in PS or PDF format to the guest
      editor (by including the email address of the corresponding author)


      If you are not sure about the suitability of a given topic or if
      you want to know more details about the special issue's intent,
      please do not hesitate to contact the guest editor.


-- All manuscripts will be peer-reviewed according to the rules of JEC.




GUEST EDITOR
============


Jingling Xue
School of Computer Science and Engineering
University of New South Wales
Sydney, NSW 2052
Australia
jxue@cse.unsw.edu.au

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