Re: How about VLIW used as RISC?

ronald@interqos.com (Ron) writes:


> We have simple scalar RISC and superscalar RISC but why there is few
> or no VLIW used as an RISC for general application?
>
> [Please try to keep this to compiler issues; comp.arch has a running
> flamefest on the Itanium that you're all welcome to join. -John]


I'll try, John. :-)


I think one of the major reasons is that VLIW relies on compilers to
statically schedule programs. While this may work fine for some types
of workloads (in particular scientific computation or graphical
stuff), it doesn't work well with modern PC-style applications. Also,
it is hard to increase parallelism in newer models of the same
instruction set without having to recompile.


An approach using a JIT compiler that collects profiling information
before compiling could work. This way, you can use an intermediate
form that has little or no scheduling information and let the JIT
compiler schedule for the actual VLIW parameters and profile. If you
regularly reprofile and recompile code, you can reschedule a program
while it runs. I believe the Transmeta processors use something like
this internally.


Torben

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