RE: Def use chain length minimization

"Naveen Sharma, Noida" <naveens@noida.hcltech.com>
31 Oct 2003 23:03:41 -0500

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Def use chain length minimization sumesh_uk@hotmail.com (2003-10-27)
RE: Def use chain length minimization naveens@noida.hcltech.com (Naveen Sharma, Noida) (2003-10-31)
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From: "Naveen Sharma, Noida" <naveens@noida.hcltech.com>
Newsgroups: comp.compilers
Date: 31 Oct 2003 23:03:41 -0500
Organization: Compilers Central
References: 03-10-122
Keywords: optimize, analysis
Posted-Date: 31 Oct 2003 23:03:41 EST

sumesh_uk@hotmail.com Wrote:


> Can some body point me to any literature on minimizing def-use
> chains so that there is no cache miss between them. In other words can
> load stores be scheduled so that they are close enough of course no
> more closer than the latency of the load.


See this work done in gcc (related to scheduling before regsiter
allocation):
http://gcc.gnu.org/ml/gcc-patches/2003-09/msg00090.html


The basic problem here was that un-restrained load-store
scheduling leads lot of spills during register-alloctaion.


I think this is in a sense related to your problem, although,
you have cache misses in mind.


Best Regards,
Naveen Sharma.

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