Re: (Once again) Branch likely instructions (MIPS R4000)

Tim Olson <fa6nxvc102@sneakemail.com>
23 Sep 2003 13:31:33 -0400

          From comp.compilers
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Re: (Once again) Branch likely instructions (MIPS R4000) vijaykrishnan@acmet.com (Vijay Krishnan) (2003-09-23)
Re: (Once again) Branch likely instructions (MIPS R4000) fa6nxvc102@sneakemail.com (Tim Olson) (2003-09-23)
| List of all articles for this month |
From: Tim Olson <fa6nxvc102@sneakemail.com>
Newsgroups: comp.compilers
Date: 23 Sep 2003 13:31:33 -0400
Organization: Compilers Central
References: 03-09-068
Keywords: architecture, optimize
Posted-Date: 23 Sep 2003 13:31:33 EDT

| How Much Am I To Lose If I Don'T Use Branch-Likely Instructions?
| My Target Is Toshiba (R4k) Tx49. The Software Is Quite Loopy & Mathematical.


None. In fact, you will probably gain performance by *not* using them.
The branch-likely instructions are somewhat misnamed: they are not
branch hints, but rather a way of saving space by not having an explicit
NOP in the delay slot of the branch.


Since they are pretty useless, the MIPS branch-likely instructions are
deprecated: implementations are required to handle them correctly, but
they aren't required to be fast. The reason they are deprecated is
that, on high-performance pipelines, conditionally squashing the result
of the delay-slot instruction is a pain in the neck.


Here's a reference to a previous comp.compilers posting back in 2000
with some more information:


      http://compilers.iecc.com/comparch/article/00-05-006


      -- Tim Olson

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