Re: What does it take to create a GCC machine description for a new processor ?

To address John's remark: the target machine has more or less an
accumulator architecture. The instruction set is quite irregular, with
a large, indirectly accessible register file, and few directly
accessible registers. It has a pipeline without interlock, just like
the MIPS. It is a 16 bit embedded controller.


Since code size and speed is quite important, I am concerned about how
GCC will perform register allocation given the indirectly accessible
register file (operands have to be moved between the few directly
accessile registers and register file with an explicit instruction).


Joris


"Joris van der Geer" <jgeer@agere.com> wrote in message
> I am assessing what it would take (time) to create a machine
> description for GCC for a new processor. It should deliver reasonably
> efficient code.
> ...
> [Depends on how similar it is to an existing description. -John]

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